Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events, which cause relatively large voltages to be applied across devices. The applied voltages from the ESD events are generally larger or greater than operational voltages typically seen and can damage the devices when these events occur.
A typical source of ESD exposure to ICs is from the charged human body (“Human Body Model”, HBM). The discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (“machine model”, MM), which can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the “charged device model” (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources.
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
Some common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
A dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. The second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Another common ESD protection scheme employs a silicon controlled rectifier (SCR) as a protection device against ESD wherein the trigger mechanism is avalanche conduction at the interface between the n-well surrounding a portion of the protection device and the p-type substrate. A highly doped region is connected to a parasitic resistor which is then connected to the protected node. The parasitic resistor and heavily doped region at the intersection between the n-well and substrate provide an additional source of current for avalanching at a lower voltage. However, such formed SCR devices are not fast enough for many semiconductor devices.